Differences between functions and Procedures in VHDL?

We are currently using the Aldec Active-VHDL software, which implementsthe full IEEE standard, for compilation and simulation of VHDL code. We use the XILINX Foundation Express for synthesis and implementationusing FPGAs. The latter software also provides for schematic entryand simulation. All of the examples in the text have been testedusing the Aldec Active-VHDL software. The synthesis examples havebeen tested using the XILINX Foundation Express along with XILINX demoboards. Some synthesis examples have also been tested using the AlteraMAX+PLUS II software along with Altera education boards. However,for the Altera software, VHDL code that implies internal tri-state bussesmust be changed to imply multiplexers.


Different synthesis tools recognisevarious different type conversion and resolution functions.
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The VHDL description willbecome technology dependent.

While this is implmentation of is not efficient (an extra variable is used to hold the value of the counter), it is perfectly valid and correct VHDL code. However, when we attempted to map it to Actel's technology by using Actmap to compile our code, the design did not work. Instead of cycling through the values 0111, 1011, 1101, 1110, the row scanner produced the values 0000, 0001, 0010, 0011.

The VHDL description however becomes technologydependent.

In order to use this book effectively, students need to have accessto appropriate VHDL software for compiling, simulating, and synthesizingVHDL code. The VHDL software should preferably implement the completeIEEE-1993 VHDL Standard. All of the examples in the book have beentested using software that conforms to this standard. Some manufacturersof FPGAs and CPLDs provide software that only implements a subset of VHDL,and many of the examples in this book will have to be modified before theycan be compiled and simulated using such software. Some softwareonly implements a synthesizable subset of the VHDL code, and delays arenot implemented. It would not be possible to do some of the timingsimulations in the book using such software.

So, your entire set of VHDL code is more like a set of Procedures for building a Digital circuit.
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Synthesis - Oregon State University

are user-defined words used to name objects in VHDL models. We have seenexamples of identifiers for input and output signals as well as the name of adesign entity and architecture body. When choosing an identifier one needs tofollow these basic rules:

Synthesis is a broad term often used to describe very different tools

As an example, consider the followingVHDL statement:When implementing this VHDL statement in an FPGA architecture, designers wouldlike to utilize vendor-provided adder hard macros, dependent on the size of n.

VHDL Reference Guide - Functions

VHDL procedures and functions greatly increase the power and
utility of the language for specifying designs. While these
constructs are being used extensively for modeling, most
VHDL synthesis tools limit their synthesis to a single
implementation style such as treating them as a component.
The authors evaluate four techniques for the synthesis of
procedures/functions and discuss their relative merits and
demerits. They examine these implementation styles in the
light of VHDL signals and wait statement semantics. The
results of the various implementation styles are shown on
several examples

Vhdl Synthesis | Hardware Description Language | Vhdl

However, even if you follow this design method, you can still end up writing un-synthesizable VHDL code. Synthesis is heavily dependant on the synthesis tools you are using. Support for VHDL functionality varies widely between vendors.

Vhdl for Synthesis - Homework Help

User-defined module generators, as opposed to using overloaded functions, allow theuse of technology specific macros (with component instantiation) for operators inVHDL or Verilog HDL.