Because you have no more a simulation/synthesis mismatch.

Currently Synplify software generates a netlist where the array ports are shifted to the top and therefore the port declaration order of the HDL netlist is different from the source code. As a result, the HDL netlist may not match the testbench assignment order. Post-synthesis and post-layout simulation fails due to the mismatch on the connection of the ports and size mismatch.

System Verilog Interface Simulation/Synthesis Mismatch

Now if they are used prior to being assigned, a mismatch may occur in simulation and synthesis.
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there is a possible simulation-synthesis-mismatch if ..

by A pitfall in the Verilog language is the treatment of unknown X values in statements, and it can cause a mismatch between the simulatedand the synthesized behaviours.

a simulation-synthesis mismatch can be the ..

We also notice there is a one-clock-cycle mismatch between implicit-style synthesis and simulation, which is, in general, solvable only for non-blocking assignment.

About the code, I am missing the point you are making about the one-hot and  synthesis / simulation mismatch.
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Useful Testbench Verilog Statements/Constructs (Simulation only) ..

Similarly, some HDLs or simulators may have glitches
in cases where others have not; for example, Verilog may have glitches
in this case, but VHDL does not.

Typically when using synthesis you design in such a way that correctness
doesn't depend on glitch behavior: all that matters is the "end" value
before moving to the next timestep.

not cause a simulation-synthesis mismatch

Let me be
definitive with some answers and summarize other important points.

Your above coding style will not cause a simulation-synthesis
mismatch.

but simulation/synthesis mismatch if assertion is not ..

in which one branch of the conditional gives one set of assignments and the other, two other assignments. If c is X, a classical Verilog simulator performs the Else assignments so that a gets the value d, and b the value e. In reality, because c is unknown, we need to consider the value of both branches being executed, by using X-Prop to evaluate the conditional for the values of 0 and 1, and then merging the two results:

Pre- and postsynthesis simulation mismatches

Identifying (and avoiding)
those cases, by the way, is a good application of "thinking hardware".

For example, in this case, there's no problem with 'a' if it is used
elsewhere as an ordinary logic input, but there may be a simulation problem
if it is used as a clock.


I don't think so in Verilog - but in VHDL there would only be one event.


As stated earlier, my response assumed that glitches were not relevant, as
should typically the case for synthesis.

Conclusions Simulation/Synthesis Mismatch ..

I could
believe that the simulator is not required to display negedge, but
prohibited from doing so?

The way I read section 5.4.1 of the standard, I see it guaranteeing
that there will be a (simulation) glitch, which is exactly the
opposite of what your response implies.

Explain to me where I am confused (where in the standard it guarantees
that the glitch is prvented).

Note, unless the synthesizer is capable of intentinally generating
gates that create glitches, it would seem that there could be a
synthesys/simulation mis-match (as the simulator might glitch and the
resulting synthesized hardware, might not).