The high-level synthesis flow (Source: Forte Design Systems)
High level synthesis of VLSI systems for low power.
David Pursley is Director of Product Marketing for . He previously held various positions as a field applications engineer, technical marketing engineer, marketing manager, and product line manager in the fields of electronic design automation and embedded computer technology. David would welcome reader’s comments on this and other articles in the high-level synthesis for low power series and on HLS generally. You can contact him at dpursley AT ForteDS DOT com.
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits.
Continuing our series on high-level synthesis (HLS) for low power design. Part Two details how HLS helps you make and evaluate architectural decisions.
Interconnect-aware Low Power High-level Synthesis
Engineers know that the decisions that have most impact on power are those taken early in the design process at the architectural level. They also likely know that high-level synthesis (HLS) allows them to quickly generate hardware from an architectural description. HLS allows engineers to rapidly assess the impact of architectural and algorithmic changes in terms of power, performance, and area at that early stage. However, this is the tip of the iceberg when it comes to exploiting HLS’ qualities for low power design. HLS tools can optimize a design for power in ways that are at best difficult when writing register transfer level (RTL) code by hand. HLS incorporates knowledge of both a design’s specific algorithms and their hardware implementations. As a result, it helps a design team reach many of the best power conclusions when creating the RTL code. Some will enhance the effectiveness of strategies typically used in a low power flow, such as clock gating and multiple threshold voltages. Others, such as those for power-aware sharing and mapping, will further reduce power consumption by changing the microarchitecture altogether. Combined, these optimizations can have a major impact across a broad range of designs. Figure 1 shows some examples. These are all for real commercial designs. They are design- and test vector-dependent, but nevertheless show how HLS delivers very strong results. The following section describes the core HLS flow and how it can be leveraged for low power design. Future articles will dive into more detail on leveraging HLS when creating and optimizing a design for low power. Specifically, they will address the following aspects of low power design with HLS.