High-Level Synthesis for FPGAs: From Prototyping to Deployment

In the following sections we will consider how these challenges affect overall productivity and the approach that S2C has taken to overcome these challenges.
Addressing FPGA-based prototyping challenges is currently offering fourth-generation FPGA-based hardware prototyping platforms. The FPGAs on the prototyping system could be from Altera or Xilinx. The boards are available in various device implementations to meet different design sizes such as a single FPGA, dual FPGA, and quad FPGA configurations. The systems are designed such that it is easy to scale the gate capacity by stacking or tiling two or more boards. The design can be configured into the prototyping system boards via JTAG, standard USB, or SD card.
Debug Visibility: In a typical design flow, the design is represented in a Hardware Description Language (HDL) – such as Verilog, SystemVerilog, or VHDL – and simulated in a RTL simulator. Most design errors are discovered and fixed in a simulation environment. In simulation, the visibility and controllability of debug signals is much greater and hence can be fixed easily. The designer can observe and fix the incorrect design behavior at the RTL level while debugging the design on a prototype means working at a gate level synthesized net-list. The synthesis process (RTL to gate level transformation) often renames the signals and sometimes completely optimizes the signals away making it difficult to correlate signals at two different abstract levels.
This year, S2C introduced its Verification Module (VM) (patent pending) to address many of these verification challenges.

High-level synthesis for fpgas from prototyping to deployment

04/04/2011 · High-Level Synthesis for FPGAs: From Prototyping to Deployment

High-level synthesis for FPGAS: from prototyping to.

Additionally, despite the fact that FPGAs can be programmed using high-level synthesis (HLS) languages such as C and OpenCL, programmers still have to be aware of many FPGA-specific optimizations to achieve reasonable performance.

In this project, we present S2FA -- an automated Spark-to-FPGA accelerator framework which generates FPGA accelerator designs from Spark RDD transformations written in Scala.

Synthesis for FPGAs: from prototyping to deployment.

Introduction Silicon process technologies have entered into the sub-30 nm realm, making it feasible to realize more than several billion transistors on a single chip. This, in turn, has made it possible to implement multiple extremely large and complex functions into a single SoC/ASIC/ASSP (hereafter referred to as SoC that applies to ASIC and ASSP) and conceive a myriad of applications catering to both consumer space and commercial usage. Furthermore, many consumer gadgets have a short life-cycle (some as low as 3 to 6 months) and are often differentiated by the software content that runs on them.
There are two primary requirements for a successful launch of these devices. First, the design must undergo thorough and prior to the design tape-out. Second, an hardware platform, representing the SoC prototype, for must be available prior to the arrival of first batch of silicon.
Silicon re-spin is not an option anymore as the mask cost alone runs into tens of millions of dollars and the lost market opportunity due to delayed product introduction may mean risking the business viability altogether.
This article first looks into various available solutions that can be used for functional verification and software development. It briefly compares various solutions and summarizes the pros and cons in using these solutions. The article focuses on FPGA-based prototyping and discusses various factors that must be taken into account to successfully implement a prototyping strategy.
Solutions for functional verification and software development There are broadly two categories of verification options available: one based on software simulation techniques and the second based on hardware platforms; the latter option is often referred to as hardware-assisted verification. The hardware platforms can be categorized as hardware acceleration, emulation, or FPGA-based prototyping. When compared in terns of ease of use, performance, and cost, each approach has its own pros and cons.
Simulation: RTL simulators are easy to setup and use, and they are relatively inexpensive. They have both high controllability and observability and hence offer 100% signal visibility into the design. The disadvantage is that the simulation performance is very low; typically in the range of 20 Hz to 30 Hz (slightly higher speeds are possible in regression mode in some simulators). Modern day designs are tens of millions of ASIC gates size, which requires the running of a very large number of test suites. Even if the simulations were run on a high-end computing machine, the effective performance is very low. Further, at this speed it is impractical to develop even low-level diagnostic type software. Also, it is not feasible to debug and verify the design in the context of the real hardware interface. Hence RTL simulators are often used only for block-level design development.
Hardware Acceleration: With hardware acceleration, the design being verified is mapped into hardware (an array of FPGAs or custom processors) to accelerate the design performance. The real bottleneck in performance is that the test bench resides in the software simulator. The performance is directly proportional to the ratio of TB (test bench) activity and the design under test (DUT) activity. To speed up performance, the TB may be required to communicate at the application level, instead of the signal level, through synthesized transactors that are mapped to the hardware along with the DUT. Transaction-based verification (TBV) minimizes the interaction of the test bench to boost performance. One major limitation of accelerators is that they verify the design in isolation and not within the context of the system. Cost is another issue that makes this approach unaffordable for multiple software and hardware developers. Typical performance for hardware acceleration is in the 250 Hz to 100 kHz range. Once again, this speed is insufficient for software development.
Emulation: Emulation allows you to map both the design and the synthesizable test bench into the hardware (this often consists of an array of FPGAs or custom processors). You can verify the emulated design in the context of the actual system using in-circuit mode. The debugging capabilities offered by emulators are powerful; however the performance can be anywhere in the range of 500 KHz to 750 KHz – possibly as high as 1.5 MHz when the design clocks are highly synchronous to each other. With these speeds, it is possible to run low-level diagnostic software, but not enough to develop application software or to bring up an operating system (that may require several hundred million CPU instructions). While emulators can be shared, the overall cost is very high – several hundred thousand to over a million dollars. This high cost of emulators prohibits creating multiple platforms (replicates) and limits the number of early users in the form of software developers and potential customers.
FPGA-Based Prototyping: The key benefits of FPGA based prototyping are low cost, high performance, and easy deployment. In addition to these benefits, the ability to interface with real-time devices allows the designer to observe the SoC prototype behavior in the context of a real system. Low system cost makes it affordable to create multiple pre-silicon hardware platforms for software development. FPGA based prototyping offers significantly high operating performance, typically in the range of 10 MHz to 80 MHz, thereby enabling verification of designs that are subjective in nature, such as video processors. Higher performance also makes it practical to develop software: device drivers, OS boot-up, and application software – which is not possible using other verification techniques. A small system footprint makes this approach easily deployable and portable to the field for demonstration and testing.
In summary their high performance and low cost makes FPGA-based rapid prototypes ideal hardware platforms for:

High-level synthesis for fpgas for prototyping to deployment - Benefits of doing homework in class
High-level synthesis for fpgas: From prototyping to deployment by Jason Cong, ..

High-Level Synthesis for FPGAs: From Prototyping to ..

The compilation of high-level languages, such as software programming languages, to FPGAs is of paramount importance for the mainstream adoption of FPGAs. An efficient compilation process will improve designer productivity and will make the use of FPGA technology viable for software programmers. When targeting the hardware resources provided by FPGAs, a compilation process usually requires a stage known as High-Level Synthesis (HLS) which is responsible for generating application specific hardware architectures from the input source code or from an intermediate representation of the input application. This chapter briefly describes HLS and its main processing stages. The chapter provides the indispensable knowledge for readers who want to follow the remaining chapters of this book.

From software threads to parallel hardware in high-level synthesis for FPGAs, ..

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High-Level Synthesis for FPGAs: From Prototyping to Deployment High-Level Synthesis for Real-Time Digital Signal Processing #L# in B. Title:

of early generations of commercial high-level synthesis ..